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| VITESSE SEMICONDUCTOR CORPORATION Preliminary Data Sheet VSC8150 Features * Integrated 2.488 Gb/s Demultiplexer * Outputs SONET/SDH Transport Overhead * Support for Multiple SONET/SDH Rates * B1 Calculation and Error Reporting 2.488Gb/s SONET/SDH Overhead Monitor * LOF/SEF Alarm Generation * Serial Data Loopthrough Output * 100 PQFP Package * Single 3.3V Supply Option General Description The VSC8150 monitors an SONET/SDH signal in order to provide section and line data for Operations, Administration, Maintenance, and Provisioning (OAM&P) at multiple SONET/SDH rates. Differential PECL clock and data input receivers and a differential data output isolate the high-speed interface. Low-speed TTL inputs and outputs allow the use of inexpensive programmable logic to perform OAM&P functions. The VSC8150 is an ideal solution for constructing a non-intrusive SONET/SDH monitoring interface when visibility of payload data is not required. Functional Description The VSC8150 high-speed interface receives recovered SONET/SDH data RXSIN +/- and clock RXSCLKIN+/- and provides a re-timed data output RXSLBOUT+/-. Internally the data is framed and SEF/LOF framing alarms generated. Incoming B1 parity is calculated and compared with the transmitted B1 value, and detected errors are output. The 27 bytes of the first STS-1 transport overhead are descrambled and output for processing. VSC8150 Functional Block Diagram DISDSCRM RESET RATESEL[1:0] SELFRDET[1:0] FRDETEN RXSLBOUT+/RXSIN+/RXSCLKIN+/1:8 DMX RXPIN[7:0] FRAMER DESCRAMBLER OVERHEAD LATCH SOHCLK SOHOUT[7:0] CONTROL & ALARM DETECTION RXFPOUT RXFRERR RXSEF RXLOF LOS RXPCLKIN B1 CHECK 311MHz INTERNAL CLOCK SOURCE B1ERR G52186-0, Rev. 3.0 10/12/98 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 Page 1 VITESSE SEMICONDUCTOR CORPORATION 2.488Gb/s SONET/SDH Overhead Monitor Preliminary Data Sheet VSC8150 NOTE: References (R#-#) or (O#-#) refer to the SONET requirement or option specification listed in Bellcore document GR-253 CORE Issue 2. Framing The frame acquisition algorithm determines the in-frame/out-of-frame status of the receiver. Out-of-frame is defined as a state where the frame boundaries of the received SONET/SDH signal are unknown, i.e. after system reset or if for some reason the receiver loses synchronization, e.g. due to `bit slips'. In-frame is defined as a state where the frame boundaries are known. Figure 1: Functional Block Diagram of Frame Acquisition Circuit FRDETEN SEFFRDET1 SELFRDET0 RXFRERR RXSEF RXLOF ERROR/ALARM DETECTION RXSIN 1:8 DMX FRAME DET FRAME SYNC. COUNTER RESYNC BYTE ALIGN OUT The receiver monitors the frame synchronization by checking for the presence of a portion of the A1/A2 framing pattern every 125uS. If one or more bit errors are detected in the expected A1/A2 framing pattern RXFRERR will be asserted for 51.44ns. If framing pattern errors are detected for four consecutive frames a Severely Errored Frame (SEF) alarm will be asserted (RXSEF active high) (R5-206) (See Figure 7and 10). The frame boundary detection/verification is based on 12, 24 or 48 bits of the A1/A2 overhead (See Figure 2) depending on the setting of the SELFRDET input (See Table 1). Frame acquisition is initiated when the FRDETEN input is held high. This control is level sensitive and the VSC8150 will continually perform frame acquisition as long as FRDETEN is held high; a suggested implementation is to short FRDETEN logically or physically to the SEF output. Such an arrangement will achieve realignment within 250uS or the receipt of two error free framing patterns (R5-208). A frame detect based on 24 bits will result in an SEF alarm at an average of no more than once every 6 minutes assuming a BER of 10-3 (R5-207). A frame detect based on 12 bits or 48 bits will result in a mean time between SEF detects of 0.43 minutes and 103 minutes respectively. Page 2 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 G52186-0, Rev. 3.0 10/12/98 VITESSE SEMICONDUCTOR CORPORATION Preliminary Data Sheet VSC8150 Table 1: Frame Detection Select Settings Function 24 bits 48 bits 12 bits Frame detection disabled 2.488Gb/s SONET/SDH Overhead Monitor SELFRDET1 1 0 0 1 SELFRDET0 0 1 0 1 Figure 2: Frame Detection Patterns 48 bits 24 bits 12 bits A1 (0xF6) A1 (0xF6) A1 (0xF6) A2 (0x28) A2 (0x28) A2 (0x28) Loss of Signal A Loss of Signal (LOS active high) input is provided to prevent noise from propagating into the overhead output logic. Logic zeros will be clocked into the device when LOS is active high, and SEF will be immediately synchronously asserted, with LOF appearing 3ms afterward. If RXSCLKIN+/- disappears before LOS is asserted the part will freeze and SEF/LOF will never appear. Loss of Frame A Loss of Frame (LOF) defect is declared (RXLOF active high) when a Severely Errored Frame (SEF) condition persists for 3ms (R6-59). The LOF state detection is based on an integrating timer to prevent sporadic errors from not asserting LOF, such as a periodic 1ms error. In the event of sporadic errors, the out of frame timer increments when RXSEF = 1. It is on hold when RXSEF = 0 and does not change state as long as this condition lasts for < 3 ms. The out of frame timer is reset to it's initial state if the RXSEF is low for > 3 ms, and an LOF defect is cancelled after an in-frame condition (RXSEF low) persists for a total of 3ms (R6-61). Multiple SONET/SDH Rate Functionality The VSC8150 supports three SONET/SDH rates: STS-48/STM-16, STS-12/STM-4, and STS-3/STM-1. The user is responsible for rate-provisioning the device by setting the two inputs RATESEL[1:0] (See Table 2). The device requires a clock rate appropriate to the selected data rate in order for internal circuitry to function correctly. LOF integration timing is 3ms regardless of the rate selected. G52186-0, Rev. 3.0 10/12/98 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 Page 3 VITESSE SEMICONDUCTOR CORPORATION 2.488Gb/s SONET/SDH Overhead Monitor Table 2: SONET/SDH Rate Select Settings Function STS-3/STM-1 STS-12/STM-4 STS-48/STM-16 Invalid Preliminary Data Sheet VSC8150 RATESEL1 0 1 0 1 RATESEL0 1 0 0 1 Descrambler Framed SONET/SDH bytes are descrambled using a frame synchronous descrambler with generating polynomial 1 + X6 + X7 and a sequence length of 127. The scrambling algorithm is reset to an all 1's state immediately following the Z0 byte ((SONET 192 x 3) | (SDH 64x9) = 577th received byte in frame). All A1, A2, and J0/Z0 bytes are not descrambled (R5-6). B1 Error Monitoring The section bit-interleaved parity (BIP-8) error detection code B1 will be calculated for every frame before de-scrambling and compared to its extracted value after de-scrambling the B1 value in the following frame (R316). If B1 errors were detected in the previous frame a series of pulses will appear on the B1ERR output, beginning approximately 60ns after the B1 byte is received. The number of pulses indicates the quantity of errored bit positions detected; the absence of pulses indicates no received B1 errors, and eight pulses would indicate the maximum number of received B1 errors. The pulses are eight parallel clocks wide (25.7nS at 2.488GHz RXSCLKIN), and spaced apart by the same amount (See figure 10). Overhead Byte Read Out Overhead bytes are descrambled (with the exception of A1, A2, and J0) and output from SOHOUT[7:0] in the order of their appearance in the frame. Only the bytes from the first STS-1 frame or the first, fourth, and seventh columns of the first STM-1 frame are presented (See Figure 6). Accompanying the data from the SOHOUT[7:0] output are the output clock SOHCLK and frame pulse RXFPOUT (See Figures 8 and 9). The SOHOUT output is undefined when SEF is high. The user should be aware that overhead data from one frame prior to the RXFRERR pulse could be corrupted and should not be used for OAM&P functions. FPGA Interface RXFPOUT is used to provide a reference point to the 27 byte sequence of overhead bytes and clocks. It is suggested that the SOHCLK be used to clock an external counter with RXFPOUT used as the counter reset. The count value can be used as the overhead byte address, and RXPOUT will reset the counter when it reaches a logical value of 27. The high order bit of this counter is useful for indicating when the B1 pulse train results can be read. A block diagram illustrates this arrangement more clearly. (See Figure 3). Page 4 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 G52186-0, Rev. 3.0 10/12/98 VITESSE SEMICONDUCTOR CORPORATION Preliminary Data Sheet VSC8150 2.488Gb/s SONET/SDH Overhead Monitor Figure 3: Suggested VSC8150 System Implementation VSC8150 B1ERR RXFPOUT FPGA 4 Bit Counter RESET Q[2:0] OAM&P B1 Count Frame Count RESET 5 Bit Counter Q4 B1 Valid SOHCLK WA[4:0] RA[4:0] SOHOUT[7:0] RXSEF RXLOF RXFRERR D[7:0] Q[7:0] OH Data 27x8 Register File LOS System Clock High Speed Interface Serial data received on the RXSIN+/- inputs is retimed on the falling edge of RXSCLKIN+/- clock and appears on the serial loopback output RXSLBOUT+/- (See Figure 11). This interface will pass data at all frequencies from DC to 2.5GHz, and does not necessarily have to retime SONET/SDH data. Inputs RXSIN+/- and RXSCLKIN+/- do not have internal termination resistors, but internal biasing resistors provide a bias voltage suitable for AC coupling (See Figure 4). In most situations these inputs will have high transition density and little DC offset. However, in cases where this does not hold, direct DC connection is possible. All serial data and clock inputs have the same circuit topology, as shown in figure 4. The reference voltage is created by a resistor divider as shown. If the input signal is driven differentially and DC-coupled to the part, the mid-point of the input signal swing should be centered about this reference voltage and not exceed the maximum allowable amplitude. For single-ended, DCcoupling operations, it is recommended that the user provides an external reference voltage which has better temperature and power supply noise rejection than the on-chip resistor divider. The external reference should have a nominal value equivalent to the common mode switch point of the DC coupled signal, and can be connected to either side of the differential gate. G52186-0, Rev. 3.0 10/12/98 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 Page 5 VITESSE SEMICONDUCTOR CORPORATION 2.488Gb/s SONET/SDH Overhead Monitor Preliminary Data Sheet VSC8150 Figure 4: High Speed Serial Clock and Data Inputs Chip Boundary VCC = 3.3V ZO CIN 1.65V 1.65V RT = ZO R| | = 1.5k VTerm CSE VEE VEE = 0V CIN TYP = 100 pF CSE TYP = 100 pF for single ended applications. (Capacitor values are selected for DI = 2.5Gb/s.) Figure 5: High Speed Output Termination VCC 50 50 100 Pre-Driver Z0 = 50 VEE Page 6 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 G52186-0, Rev. 3.0 10/12/98 VITESSE SEMICONDUCTOR CORPORATION Preliminary Data Sheet VSC8150 2.488Gb/s SONET/SDH Overhead Monitor The high speed data and clock output drivers consist of a differential pair designed to drive a 50 transmission line. The transmission line should be terminated with a 100 resistor at the load between true and complement outputs (See Figure 5). No connection to a termination voltage is required. The output driver is back terminated to 50 on-chip, providing a snubbing of any reflections. If used single-ended, the high speed output driver must still be terminated differentially at the load with a 100 resistor between true and complement outputs. Figure 6: Transport Overhead STS-48(48) STS-48(3) STS-48(2) STS-48(1) Framing A1 Framing A2 Orderwire E1 Datacom D2 Pointer H2 APS K1 Datacom D5 Datacom D8 Datacom D11 REI-L M0 STS-48 J0 User F1 Datacom D3 Pointer Action H3 APS K2 Datacom D6 Datacom D9 Datacom D12 Orderwire E2 STM-1(1) BIP-8 STS-48 B1 Datacom D1 Pointer H1 BIP-8 STS-48(1) B2 Datacom D4 Datacom D7 Datacom D10 Sync S1 Note: Only bytes from the first STS-1 of the SONET signal are output from the SOHOUT[7:0] port. G52186-0, Rev. 3.0 10/12/98 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 Page 7 VITESSE SEMICONDUCTOR CORPORATION 2.488Gb/s SONET/SDH Overhead Monitor Preliminary Data Sheet VSC8150 Figure 7: Functional Framing Timing Diagram (STS-48/STM-16 Mode) RXSCLKIN RXSIN b7 b6 b5 b4 b3 b2 b1 b0 RXPCLKIN RXPIN[7:0] J0 J0 J0 J0 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 RXFPOUT RXFRERR RXSEF Figure 8: Functional Overhead Readout Timing Z2 SOHOUT[7:0] E2 A1 A2 J0 B1 E1 F1 SOHCLK RXFPOUT Page 8 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 G52186-0, Rev. 3.0 10/12/98 VITESSE SEMICONDUCTOR CORPORATION Preliminary Data Sheet VSC8150 AC Timing Characteristics Figure 9: Overhead Output Timing Diagram SOHOUT[7:0] 2.488Gb/s SONET/SDH Overhead Monitor E2 A1 TOHSU A2 TOHH C1/J0 SOHCLK TOHCLKW RXFPOUT TFPSU TFPW Table 3: Overhead Output Timing (STS-48/STM-16 Mode) Parameter TOHSU TOHH TOHCLKW TFPSU TFPW Description Overhead output setup time with respect SOHCLK Overhead output hold time with respect SOHCLK Overhead output clock period Frame pulse setup time with respect to SOHCLK Frame pulse width Min -- -- -- -- -- Typ 75 75 154 90 50 Max -- -- -- -- -- Units ns ns ns ns ns Note: Generated Waveforms are synchronous and assume a 2.488GHz RXSCLKIN signal. Table 4: Overhead Output Timing (STS-12/STM-4 Mode) Parameter TOHSU TOHH TOHCLKW TFPSU TFPW Description Overhead output setup time with respect SOHCLK Overhead output hold time with respect SOHCLK Overhead output clock period Frame pulse setup time with respect to SOHCLK Frame pulse width Min -- -- -- -- -- Typ 75 75 154 116 50 Max -- -- -- -- -- Units ns ns ns ns ns Note: Generated Waveforms are synchronous and assume a 622MHz RXSCLKIN signal. Table 5: Overhead Output Timing (STS-3/STM-1 Mode) Parameter TOHSU TOHH TOHCLKW TFPSU TFPW Description Overhead output setup time with respect SOHCLK Overhead output hold time with respect SOHCLK Overhead output clock period Frame pulse setup time with respect to SOHCLK Frame pulse width Min -- -- -- -- -- Typ 100 50 154 150 50 Max -- -- -- -- -- Units ns ns ns ns ns Note: Generated Waveforms are synchronous and assume a 155MHz RXSCLKIN signal. G52186-0, Rev. 3.0 10/12/98 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 Page 9 VITESSE SEMICONDUCTOR CORPORATION 2.488Gb/s SONET/SDH Overhead Monitor Preliminary Data Sheet VSC8150 Figure 10: Framing and B1 Error Output Timing TFPW RXFPOUT TFERRPW TFERRSU TSEFSU RXFRERR RXSEF TB1SU TB1PWH TB1PWL B1ERR Note: Waveforms not to scale Table 6: Framing and B1 Error Output Timing (STS-48/STM-16 Mode) Parameter TFPW TFERRSU TFERRPW TSEFSU TB1SU TB1PWH TB1PWL Frame Pulse Width Frame Boundary Error delay with respect to RXFPOUT Frame Boundary Error pulse width high SEF transition delay time with respect to RXFPOUT B1 Pulse train delay with respect to RXFPOUT B1 error pulse width high B1 error pulse width low Description Min -- -- -- -- -- -- -- Typ 51.4 61.2 25.7 48.3 14 25.7 25.7 Max -- -- -- -- -- -- -- Units ns ns ns ns s ns ns Note: Generated Waveforms are synchronous and assume a 2.488GHz RXSCLKIN signal. Table 7: Framing and B1 Error Output Timing (STS-12/STM-4 Mode) Parameter TFPW TFERRSU TFERRPW TSEFSU TB1SU TB1PWH TB1PWL Frame Pulse Width Frame Boundary Error delay with respect to RXFPOUT Frame Boundary Error pulse width high SEF transition delay time with respect to RXFPOUT B1 Pulse train delay with respect to RXFPOUT B1 error pulse width high B1 error pulse width low Description Min -- -- -- -- -- -- -- Typ 51.4 64.4 51.4 51.4 14 103 103 Max -- -- -- -- -- -- -- Units ns ns ns ns s ns ns Note: Generated Waveforms are synchronous and assume a 622MHz RXSCLKIN signal. Page 10 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 G52186-0, Rev. 3.0 10/12/98 VITESSE SEMICONDUCTOR CORPORATION Preliminary Data Sheet VSC8150 Table 8: Framing and B1 Error Output Timing (STS-3/STM-1 Mode) Parameter TFPW TFERRSU TFERRPW TSEFSU TB1SU TB1PWH TB1PWL Frame Pulse Width Frame Boundary Error delay with respect to RXFPOUT Frame Boundary Error pulse width high SEF transition delay time with respect to RXFPOUT B1 Pulse train delay with respect to RXFPOUT B1 error pulse width high B1 error pulse width low 2.488Gb/s SONET/SDH Overhead Monitor Description Min -- -- -- -- -- -- -- Typ 51.4 0 51.4 103 13.96 409 409 Max -- -- -- -- -- -- -- Units ns ns ns ns s ns ns Note: Generated Waveforms are synchronous and assume a 155MHz RXSCLKIN signal. Figure 11: Serial Data Input Timing Diagram TRXSCLKIN RXSCLKINRXSCLKIN+ TRXSSU RXSIN+ RXSINTRXSH TRXSLBOUT RXSLBOUT+ RXSLBOUT- Table 9: Serial Data Input Timing Parameter TRXSCLKIN TRXSSU TRXSH TRXSLBOUT Description Serial Receive clock period Serial Receive input data RXSIN setup time with respect to falling edge of RXSCLKIN+ Serial Receive input data RXSIN hold time with respect to falling edge of RXSCLKIN+ Propagation delay from falling edge of RXSCLKIN+ Min 401.9 100 75 430 Typ - Max 820 Units ps ps ps ps G52186-0, Rev. 3.0 10/12/98 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 Page 11 VITESSE SEMICONDUCTOR CORPORATION 2.488Gb/s SONET/SDH Overhead Monitor Preliminary Data Sheet VSC8150 DC Characteristics Table 10: High-Speed Differential ECL Inputs and Outputs (HSECL) Parameter Description Output differential voltage (Peak to Peak, Single-ended) Output common-mode voltage Output Rise / Fall Output Impedance Input differential voltage Min 550 Typ - Max 1200 Units mV Conditions Load = 100 Ohms across RXSLBOUT+/- at receiver Load = 100 Ohms across RXSLBOUT+/- at receiver -- -- AC Coupled, internally biased to VCC/2 VOD VOCM Trf RO VID 2100 40 200 100 - 3000 60 mV ps ohms mV Note: HSECL inputs are NOT terminated on chip (high impedance inputs). Table 11: TTL Inputs and Outputs Parameter Description Min 2.4 0 2.0 0 -50 Typ - Max 0.4 VCC + 1.0V 0.8 500 - Units V V V V uA uA Conditions IOH = -8mA IOL = 8mA -- -- VIN = 2.4V VIN = 0.4V VOH VOL VIH VIL IIH IIL Output HIGH voltage Output LOW voltage Input HIGH voltage Input LOW voltage Input HIGH current Input LOW current Table 12: Power Supply Currents (VMM = VCC = +3.3V, Outputs Open) Parameter ITTL PD Power supply current from VCC Power dissipation Description (Max) 850 2.95 Units mA W Table 13: Power Supply Currents (VMM = +2.0V, VCC = +3.3V, Outputs Open) Parameter ITTL IMM PD Power supply current from VCC Power supply current from VMM Power dissipation Description (Max) 420 430 2.35 Units mA mA W Page 12 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 G52186-0, Rev. 3.0 10/12/98 VITESSE SEMICONDUCTOR CORPORATION Preliminary Data Sheet VSC8150 Absolute Maximum Ratings 2.488Gb/s SONET/SDH Overhead Monitor Power Supply Voltage (VCC) Potential to GND ............................................................................ -0.5 V to +4.3 V TTL Input Voltage Applied ...........................................................................................................-0.5 V to + 5.5V ECL Input Voltage Applied ................................................................................................... +0.5 V to VTT -0.5 V Output Current (IOUT) ................................................................................................................................... 50 mA Case Temperature Under Bias (TC) ................................................................................................-55o to + 125oC Storage Temperature (TSTG)............................................................................................................-65o to + 150oC Note: Caution: Stresses listed under "Absolute Maximum Ratings" may be applied to devices one at a time without causing permanent damage. Functionality at or exceeding the values listed is not implied. Exposure to these values for extended periods may affect device reliability. Recommended Operating Conditions Power Supply Voltages (VCC)...............................................................................................................+3.3V 5 % Power Supply Voltages (VMM) ..............................................................................................................+2.0V 5 % Commercial Operating Temperature Range (T) .................................................................................... 0o to 85oC Notes: (1) Lower limit of specification is ambient temperature and upper limit is case temperature. (2) Customer may require cooled/heatsink environment to meet thermal requirements of 100PQFP. (3) Contact factory for package thermal performance information. ESD Ratings Proper ESD procedures should be used when handling this product. The VSC8150 is rated to the following ESD voltages based on the human body model: 1. All pins are rated at or above 1500V. G52186-0, Rev. 3.0 10/12/98 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 Page 13 VITESSE SEMICONDUCTOR CORPORATION 2.488Gb/s SONET/SDH Overhead Monitor Preliminary Data Sheet VSC8150 VSC8150 Package Pin Diagram SELFRDET0 SELFRDET1 RATESEL0 RATESEL1 RXFRERR RXFPOUT SOHOUT7 FRDETEN RXLOF RXSEF B1ERR VMM VMM TEST VCC VCC VCC VCC 77 VEE VEE VEE VEE 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 76 LOS NC NC VCC VEE VMM VCC VCC NC NC VCC RXSCLKIN+ RXSCLKIN- VEE RXSIN+ RXSIN- VEE RXSLBOUT+ RXSLBOUT- VCC NC NC VCC VCC VMM VEE VCC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 VCC VMM VCC VEE SOHOUT6 SOHOUT5 VEE SOHOUT4 SOHOUT3 VCC VEE SOHCLK SOHOUT2 VCC VEE SOHOUT1 SOHOUT0 VEE NC NC VCC VCC VMM VCC TEST 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 VCC DISDSCRM TEST TEST VCC VCC TEST TEST VEE TEST TEST VMM TEST TEST VCC VCC TEST TEST VMM RESET VEE TEST TEST VCC Page 14 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 NC 50 G52186-0, Rev. 3.0 10/12/98 VITESSE SEMICONDUCTOR CORPORATION Preliminary Data Sheet VSC8150 Package Pin Description Table 14: Pin Definitions Signal VCC VEE VMM VCC VCC NC NC VCC RXSCLKIN+ RXSCLKINVEE RXSIN+ RXSINVEE RXSLBOUT+ RXSLBOUTVCC NC NC VCC VCC VMM VEE VCC TEST TEST VCC VCC TEST TEST VEE TEST TEST VMM TEST TEST 2.488Gb/s SONET/SDH Overhead Monitor Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 26 27 28 29 30 31 32 33 34 35 36 37 I/O PWR PWR PWR PWR PWR - - PWR I I PWR I I PWR O O PWR - - PWR PWR PWR PWR PWR I I PWR PWR I I PWR I I PWR I I Level +3.3V GND +2.0V +3.3V +3.3V - - +3.3V PECL PECL GND PECL PECL GND PECL PECL +3.3V - - +3.3V +3.3V +2.0V GND +3.3V GND GND +3.3V +3.3V GND GND GND GND GND +2.0V GND GND Pin Description Leave Unconnected Leave Unconnected Demux CLK Input Demux CLK Input Demux DATA Input Demux DATA Input Demux DATA Output Demux DATA Output Leave Unconnected Leave Unconnected Test Input Test Input Test Input Test Input Test Input Test Input Test Input Test Input G52186-0, Rev. 3.0 10/12/98 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 Page 15 VITESSE SEMICONDUCTOR CORPORATION 2.488Gb/s SONET/SDH Overhead Monitor Table 14: Pin Definitions Signal VCC VCC TEST TEST VMM RESET DISDSCRM VEE TEST TEST VCC VCC NC TEST VCC VMM VCC VCC NC NC VEE SOHOUT0 SOHOUT1 VEE VCC SOHOUT2 SOHCLK VEE VCC SOHOUT3 SOHOUT4 VEE SOHOUT5 SOHOUT6 VEE VCC VMM VCC Preliminary Data Sheet VSC8150 Pin 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 I/O PWR PWR I I PWR I I PWR I I PWR PWR - I PWR PWR PWR PWR -- -- PWR O O PWR PWR O O PWR PWR O O PWR O O PWR PWR PWR PWR Level +3.3V +3.3V GND GND +2.0V TTL TTL GND GND GND +3.3V +3.3V - GND +3.3V +2.0V +3.3V +3.3V NC NC GND TTL TTL GND +3.3V TTL TTL GND +3.3V TTL TTL GND TTL TTL GND +3.3V +2.0V +3.3V Pin Description Test Input Test Input Active High (Tie to GND) Descrambler Disable Test Input Test Input Leave Unconnected Test Input Test Output Test Output Overhead Output Bus Overhead Output Bus Overhead Output Bus Overhead Output Clock Overhead Output Bus Overhead Output Bus Overhead Output Bus Overhead Output Bus Page 16 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 G52186-0, Rev. 3.0 10/12/98 VITESSE SEMICONDUCTOR CORPORATION Preliminary Data Sheet VSC8150 Table 14: Pin Definitions Signal LOS VCC VEE SOHOUT7 NC VEE RXLOF RXSEF VMM NC B1ERR VEE VCC RXFRERR RXFPOUT VMM RATESEL1 FRDETEN VEE SELFRDET1 SELFRDET0 VCC VCC RATESEL0 TEST 2.488Gb/s SONET/SDH Overhead Monitor Pin 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 I/O I PWR PWR O - PWR O O PWR - O PWR PWR O O PWR I I PWR I I PWR PWR I I Level TTL +3.3V GND TTL - GND TTL TTL +2.0V - TTL GND +3.3V TTL TTL +2.0V TTL TTL GND TTL TTL +3.3V +3.3V TTL GND Pin Description Loss of Signal Overhead Output Bus Leave Unconnected Loss of Frame Severely Errored Frame Leave Unconnected B1 Error Pulse Output Frame Error Detect Frame Pointer Output STS-12/STM-4 Select Frame Detect Enable Frame Mode Select Frame Mode Select STS-3/STM-1 Select Test Input Table 15: Power Supply Summary Signal VCC Pin 1,4,5,8,17,20,21, 24,28,29,38,39,48, 49,52,54,55,62,66, 73,75,77,88,97,98 3,22,35,42,53,74, 84,91 2,11,14,23,32,45, 58,61,65,69,72,78, 81,87,94 I/O PWR Level +3.3V Pin Description VMM PWR +2.0V Connect to +3.3V for single supply configuration VEE PWR GND G52186-0, Rev. 3.0 10/12/98 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 Page 17 VITESSE SEMICONDUCTOR CORPORATION 2.488Gb/s SONET/SDH Overhead Monitor Preliminary Data Sheet VSC8150 100 PQFP Package Drawings Package Information EXPOSED HEATSINK 6.86 .50 DIA. D D1 Key A A1 A2 D D1 E E1 E mm 2.35 0.25 2.00 17.20 14.00 17.20 14.00 .88 .50 .22 0-7 .30 .20 Tolerance MAX MAX +.10/-.05 .25 .10 .25 .10 +.15/-.10 BASIC .05 TYP TYP E1 L e b R R1 10 o TYP HEATSINK INTRUSION .0127 MAX A2 10 o TYP A e R R1 6 4 A 0.25 A1 0.17 MAX NOTES: (1) Drawings not to scale. (2) All units in millimeters unless otherwise noted Package #: 101-318-3 Issue #: 1 L b Page 18 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 G52186-0, Rev. 3.0 10/12/98 VITESSE SEMICONDUCTOR CORPORATION Preliminary Data Sheet VSC8150 Ordering Information 2.488Gb/s SONET/SDH Overhead Monitor The order number for this product is formed by a combination of the device number, and package type. VSC8150 Device Type VSC8150: 2.488Gb/s Overhead Monitor Package QQ: 100 PQFP, 14x14mm Body Notice This document contains preliminary information about a new product in the preproduction phase of development. The information in this document is based on initial product characterization. Vitesse reserves the right to alter specifications, features, capabilities, functions, manufacturing release dates, and even general availability of the product at any time. The reader is cautioned to confirm this datasheet is current prior to using it for design. Warning Vitesse Semiconductor Corporation's product are not intended for use in life support appliances, devices or systems. Use of a Vitesse product in such applications without the written consent is prohibited. G52186-0, Rev. 3.0 10/12/98 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 Page 19 VITESSE SEMICONDUCTOR CORPORATION 2.488Gb/s SONET/SDH Overhead Monitor Preliminary Data Sheet VSC8150 Page 20 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 G52186-0, Rev. 3.0 10/12/98 |
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